The present disclosure relates to the breakdown of dielectric material positioned laterally between a gate and a source/drain contact in a non-planar field effect transistor (FET) and, particularly, to a test structure for acquiring data regarding such dielectric breakdown, a method of forming the test structure, and an associated testing method.
As field effect transistor (FET) dimensions continue to be scaled and new FET configurations are developed, dielectric breakdown failure mechanisms that can significantly impact FET reliability must be considered by designers in assessing reliability. Such dielectric breakdown failure mechanisms include gate dielectric breakdown (i.e., breakdown of the gate dielectric layer between a gate conductor layer and a channel region of a FET) as well as lateral dielectric breakdown (i.e., breakdown of the dielectric material between the FET gate and an adjacent source/drain contact). With regard specifically to lateral dielectric breakdown, the scaling of FET dimensions has lead to corresponding scaling of the width of the spaces between the gate and the source/drain contacts, thereby increasing the risk of lateral dielectric breakdown. Furthermore, various different process variations (e.g., overlay variations, reactive ion etch variations, chemical mechanical polishing (CMP) variations, gate size variations, contact size variations, etc.) can result in chip-to-chip and across-chip variations in the width of the spaces between the gate and source/drain contacts in FETs manufactured according to a given FET design. Therefore, it is particularly important for designers to be able to accurately assess lateral dielectric breakdown for the given FET design and, thereby to assess its impact on FET reliability. Recently, test structures have been developed that allow lateral dielectric breakdown to be assessed in planar FETs without the influence of gate dielectric breakdown; however, such test structures are not adequate for use with non-planar FETs.